(1) Field of the Invention
This invention relates to the formation of field oxide isolation regions using local oxidation of silicon and more specifically to the use of nitride spacers to provide a smooth surface on the field oxide to improve step coverage of subsequent process steps.
(2) Description of the Related Art
U.S. Pat. No. 5,399,520 to Jang describes the use of nitride films and trenches formed in the integrated circuit substrate to form field oxide isolation regions. The processes and structure are different from the invention of this Patent Application.
U.S. Pat. No. 5,393,694 to Mathews describes the use of polysilicon to fill recesses in the field oxide isolation regions. The processes and structure are different from the invention of this Patent Application.
A paper entitled "Reverse Elevated Source/Drain (RESD) MOSFET for Deep Submicron CMOS," by J. R. Pfiester et al., IEDM 92, pages 885-888 describes the use of disposable nitride spacers to define selective silicon offset from the gate edge prior to Lightly Doped Drain implantation in a new Reverse Elevated Source/Drain CMOS device.
A paper entitled "IMPACT OF LDD SPACER REDUCTION ON MOSFET PERFORMANCE FOR SUB-.mu.m GATE/SPACE PITCHES," by Carlos Mazure et al., IEDM 92, pages 893-896 describes the use of nitride spacers and LPCVD TEOS spacers in forming MOSFET devices having sub micron gate/space pitches.
The invention of this Patent Application uses nitride spacers formed on the sidewalls of field oxide regions to fill the recesses formed in the field oxide by over etching thereby providing a smooth surface for subsequent process steps.